The addition of low-power customized FSM encoding needs only one additional design step requiring only small amount of coding the effort overhead is nearly zero. The methodology is also independent on the designed device and fully reusable between projects. Described methodology allows to reduce device power consumption and is compatible with all design tools. The advantage of the described approach is a seamless integration of an FSM encoding algorithm into a standard RTL ASIC design flow. Text summarizes current techniques and presents a methodo-logy for design of FSMs with reduced power consumption targeted to low-power smart sensors and RFID devices. This contribution focuses on integration of low power design approaches for synchronous Finite State Machi-nes (FSMs) designs into a standard RTL digital design flow.
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March 2023
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